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Integrated Device Technology, Inc.
BiCMOS StaticRAM 240K (16K x 15-BIT) CACHE-TAG RAM For PowerPCTM and RISC Processors
IDT71216
FEATURES:
* 16K x 15 Configuration - 12 TAG Bits - 3 Separate I/O Status Bits (Valid, Dirty, Write Through) * Match output uses Valid bit to qualify MATCH output * High-Speed Address-to-Match comparison times - 8/9/10/12ns over commercial temperature range * TA circuitry included inside the Cache-Tag for highest speed operation * Asynchronous Read/Match operation with Synchronous Write and Reset operation * Separate WE for the TAG bits and the Status bits * Separate OE for the TAG bits, the Status bits, and TA * Synchronous RESET pin for invalidation of all Tag entries * Dual Chip selects for easy depth expansion with no performance degredation * I/O pins both 5V TTL and 3.3V LVTTL compatible with VCCQ pins * PWRDN pin to place device in low-power mode * Packaged in a 80-pin Thin Plastic Quad Flat Pack (TQFP)
DESCRIPTION:
The IDT71216 is a 245,760-bit Cache Tag StaticRAM, organized 16K x 15 and designed to support PowerPC and other RISC processors at bus speeds up to 66MHz. There are twelve common I/O TAG bits, with the remaining three bits used as status bits. A 12-bit comparator is on-chip to allow fast comparison of the twelve stored TAG bits and the current Tag input data. An active HIGH MATCH output is generated when these two groups of data are the same for a given address.
This high-speed MATCH signal, with tADM as fast as 8ns, provides the fastest possible enabling of secondary cache accesses. The three separate I/O status bits (VLD, DTY, and WT) can be configured for either dedicated or generic functionality, depending on the SFUNC input pin. With SFUNC LOW, the status bits are defined and used internally by the device, allowing easier determination of the validity and use of the given Tag data. SFUNC HIGH releases the defined internal status bit usage and control, allowing the user to configure the status bit information to fit his system needs. A synchronous RESET pin, when held LOW at a rising clock edge, will reset all status bits in the array for easy invalidation of all Tag addresses. The IDT71216 also provides the option for Transfer Acknowledge (TA) generation within the cache tag itself, based upon MATCH, VLD bit, WT bit, and external inputs provided by the user. This can significantly simplify cache controller logic and minimize cache decision time. Match and Read operations are both asynchronous in order to provide the fastest access times possible, while Write operations are synchronous for ease of system timing. The IDT71216 uses a 5V power supply on Vcc, with separate VCCQ pins provided for the outputs to offer compliance with both 5.0V TTL and 3.3V LVTTL Logic levels. The PWRDN pin offers a low-power standby mode to reduce power consumption by 90%, providing significant system power savings. The IDT71216 is fabricated using IDT's high-performance, high-reliability BiCMOS technology and is offered in a spacesaving 80-pin Thin Plastic Quad Flat Pack (TQFP) package.
PIN DESCRIPTIONS
A0 - A13 Address Inputs Chip Selects Write Enable - Tag Bits Write Enable - Status Bits Output Enable - Tag Bits Output Enable - Status Bits Status Bit Reset Powerdown Mode Control Pin Status Bit Function Control Pin Read/Write Input from Processor Valid Bit / S1 Bit Input Dirty Bit / S2 Bit Input Write Through Bit / S3 Bit Input Input Input Input Input Input Input Input Input Input Input Input Input Input CLK TAH System Clock Input Input Input Input Output I/O Output Output Output Output Pwr QPwr Gnd
3067 tbl 01 The IDT logo is a registered trademark and CacheRAM is a trademark of Integrated Device Technology, Inc. PowerPC is a trademark of International Business Machines, Inc.
CS1, CS2 WET WES OET OES RESET PWRDN
SFUNC TT1 VLDIN / S1IN DTYIN / S2IN WTIN / S3IN
TAOE TAIN TA
TAG0 - TAG11 VLDOUT / S1OUT DTYOUT / S2OUT WTOUT / S3OUT MATCH VCC VCCQ VSS
TA Force High TA Output Enable Additional TA Input
Transfer Acknowledge Tag Data Input/Outputs Valid Bit / S1 Bit Output Dirty Bit / S2 Bit Output Write Through Bit / S3 Bit Output Match +5V Power Output Buffer Power Ground
COMMERCIAL TEMPERATURE RANGE
(c)1996 Integrated Device Technology, Inc.
AUGUST 1996
DSC-3067/3
14.3
1
IDT71216 BiCMOS 16K x 15 CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
VLDIN / S1IN
PWRDN
TAG11
TAG10
RESET
OES OET TAOE
CS1 WET WES
CS2
CLK
VSS
VSS VSS VSS VSS DTYIN / S2IN WTIN / S3IN A0 A1 A2 VCC VSS A3 A4 A5 A6 A7 VSS VSS VSS VSS
1
80
TAG9
VSS VSS VSS TAG8 TAG7 TAG6 VLDOUT / S1OUT VCCQ VSS
VCCQ
VCC
VCC
VSS
VSS
PN80-1
TA
MATCH VSS VCCQ WTOUT / S3OUT TAG5 TAG4 NC VSS VSS VSS
A10
A11
DTYOUT / S2OUT
A12
TT1
A13
VCC
SFUNC
TAG0 VSS
TAG1
VCCQ
VCC
TAG2
TAG3
VSS
TAH
TAIN
A8
A9
3067 drw 01
TQFP TOP VIEW
14.3
2
IDT71216 BiCMOS 16K x 15 CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
ADDR (0:13) Reg 0 1 16K x 12 MEMORY TAG BITS 16K x 3 MEMORY STATUS BITS
CS1
CS2 Reg DataIN Register SA SA DataIN Register VLD/S1IN DLY/S2IN WT/S3IN
TAG (0:11)
OET
WRITE (pos) PULSE GENERATOR VLD/S1OUT DLY/S2OUT WT/S3OUT
WET WES
CLK
Reg
RESET (neg) PULSE GENERATOR COMPARE
OES
RESET PWRDN
SFUNC MATCH TT1 TAH
TAIN
TA
Reg
TAOE
3067 drw 02
14.3
3
IDT71216 BiCMOS 16K x 15 CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
TRUTH TABLES CHIP SELECT, RESET, AND POWER-DOWN FUNCTIONS(1, 2) CS1 CS2 RESET PWRDN CLK WET WES TAOE TAG VLDOUT DTYOUT WTOUT MATCH CHIP SELECT FUNCTION
H X L X L H X X X H H H X X X X X X X X X X X X Hi-Z Hi-Z - Hi-Z Hi-Z - Hi-Z Hi-Z - Hi-Z Hi-Z - Hi-Z Hi-Z - Hi-Z Hi-Z - Deselected Deselected Selected Active Active Active
TA
OPERATION POWER
RESET FUNCTION
L L H X X X H H X L X X L L L L L L H H H H H H H H H H L X H H H H X L L H X X X X Hi-Z Hi-Z Hi-Z Hi-Z - - L(3) L(3) Hi-Z Hi-Z - - L(3) L(3) Hi-Z Hi-Z - - L(3) L(3) Hi-Z Hi-Z - - L(3) L(3) Hi-Z Hi-Z - - H Hi-Z Hi-Z Hi-Z - - Reset Status Reset Status Reset Status Reset Status Not Allowed Not Allowed Active Active Active Active - -
POWER-DOWN FUNCTION
X X X L X H H X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Power-down Standby
3067 tbl 02
NOTES: 1. "H" = VIH, "L" = VIL, "X" = don't care, "-" = unrelated. 2. OET, OES, TT1, TAH, TAIN and SFUNC are "X" for this table. 3. OES is LOW.
READ AND WRITE FUNCTIONS(1, 2)
OET OES WET WES
READ FUNCTION
L X H X X L X H H X X X X X X X
CLK
TT1
TAG VLDIN
DTYIN WTIN
VLDOUT DTYOUT WTOUT
MATCH
OPERATION
X X X X
X X X X
DOUT - Hi-Z -
- - - -
- - - -
- - - -
- DOUT - Hi-Z
- DOUT - Hi-Z
- DOUT - Hi-Z
DOUT DOUT DOUT DOUT
Read TAG I/O Read Status Bits TAG I/O Disable Status Disabled
WRITE FUNCTION
H L X X X X L H L L X X X X L L X X X X DIN - - - - - DIN DIN - - DIN DIN - - DIN DIN DOUT - DOUT - DOUT - L - L L Write TAG I/O Not Allowed Write Status Bits Write Status Bits
3067 tbl 03
DOUT(3) DOUT(3) DOUT(3) Hi-Z Hi-Z Hi-Z
NOTES: 1. "H" = VIH, "L" = VIL, "X" = don't care, "-" = unrelated. 2. This table applies when CS1 is LOW and CS2, RESET, and PWRDN are HIGH. TAOE, TAH, TAIN and SFUNC are "X" for this table. 3. DOUT in this case is the same as DIN; that is, the input data is written through to the outputs during the write operation.
14.3
4
IDT71216 BiCMOS 16K x 15 CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
TRUTH TABLES (CONT.) MATCH FUNCTION(1, 2, 3) CS1 CS2 SFUNC OET WET WES
H X L L L L L L L X L H H H H H H H X X X X X X L L H X X X L H X H H H X X X H L X H H H X X X X X L H H H
TAG Hi-Z Hi-Z - DOUT DIN - TAGIN TAGIN TAGIN
VLD(4) DTY(4) WT(4) MATCH - - - - - DIN L H X - - - - - DIN - - - - - - - - DIN - - - Hi-Z Hi-Z DOUT L L L L M M
OPERATION Deselected Deselected Selected Read Tag I/O Write Tag I/O Write Status Bits Invalid Data - Dedicated Status Bits Match - Dedicated Status Bits Match - Generic Status Bits
3067 tbl 04
NOTES: 1. "H" = VIH, "L" = VIL, "X" = don't care, "-" = unrelated. 2. M = HIGH if TAGIN equals the memory contents at that address; M = LOW if TAGIN does not equal the memory contents at that address. 3. PWRDN and RESET are HIGH for this table. TT1, TAH, TAOE, TAIN, OES, and CLK are "X". 4. This column represents the stored memory cell data for the given Status bit at the selected address.
TA FUNCTION(1, 2, 3, 5)
TAOE
H L L L L L L L L L L L
TAIN(6) OET WET WES
X L H H H H H H H H H H X X L X X X X X H H H H X X X L X X X X H H H H X X X X L X X X H H H H
TAH X X X X X H X X L L L L
TT1 SFUNC X X X X X X X L X H X X X X X X X X L L L L L H
VLD(4) DTY(4) WT(4) TAG MATCH X X X X DIN X L X H H H X - - - - DIN - - - - - - - X X X X DIN X X H L X X X - - DOUT DIN - - - - TAGIN TAGIN TAGIN TAGIN - X L L L X L X M M M M
TA
Hi-Z L H H H H H H
OPERATION
TA Disabled
External TA Input (7) Read TAG Write TAG Write Status Force TA HIGH Invalid TAG Write Through Compare Compare Compare Compare
M M M M
NOTES: 3067 tbl 05 1. "H" = VIH, "L" = VIL, "X" = don't care, "-" = unrelated. 2. M = HIGH if TAGIN equals the memory contents at that address; M = LOW if TAGIN does not equal the memory contents at that address. 3. PWRDN and RESET are HIGH for this table. CLK and OES are "X". 4. This column represents the stored memory cell data for the given Status bit at the selected address. 5. CS1 is LOW, CS2 is HIGH for this table. 6. TAIN is a synchronous input; thus the inputs noted in the table must be applied during a rising CLK edge. 7. TAIN will be a factor in determining the TA output in all cases except when TAH is HIGH and there is a valid MATCH. In that case, TA will be LOW(Valid).
14.3
5
IDT71216 BiCMOS 16K x 15 CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC VCCQ VCCQ VSS VIH VIHQ VIL Parameter Supply Voltage 5V Output Buffers 3.3V Output Buffers Supply Ground Input High Voltage I/O High Voltage Input Low Voltage Min. 4.75 4.75 3.0 0 2.2 2.2 -0.5(1) Typ. 5.0 5.0 3.3 0 3.0 3.0 -- Max. 5.25 5.25 3.6 0
VCC+0.3 VCCQ+0.3
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Unit V V V V V V V TA TBIAS TSTG PT IOUT VTERM Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value -0.5 to +7.0(2) -0 to +70 -65 to +135 -65 to +150 1.7 20 Unit V C C C W mA
0.8
NOTE: 3067 tbl 06 1. VIL (min.) = -1.5V for pulse width of less than 10ns, once per cycle.
CAPACITANCE
(TA = +25C, f = 1.0 MHz)
Symbol CIN CTAG COUT Parameter(1) Input Capacitance TAG Input/Output Capacitance Output Capacitance Condition VIN = 0V VI/O = 0V VOUT = 0V Max. 5 7 7 Unit pF pF pF
NOTES: 3067 tbl 08 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabilty. 2. VIN should not exceed Vcc+0.5V. All pins should not exceed 7.0V. VCCQ should never exceed VCC, and VCC should never exceed VCCQ + 4.0V.
NOTE: 3067 tbl 07 1. This parameter is determined by device characterization but is not production tested.
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(VCC = 5.0V 5%, VCCQ = 5.0V 5% OR 3.3V 0.3V)
Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Test Condition VCC = Max., VIN = 0V to VCC Min. -- -- -- 2.4 Max. 5 5 0.4 -- Unit A A V V
3067 tbl 09
CS1 VIH, CS2 VIL, OE VIH, VCC = Max.
VOUT = 0V to VCCQ, VCCQ = Max. IOL = 4mA, VCC = Min. IOH = -4mA, VCC = Min.
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1, 2) (VCC = 5.0V 5%)
Symbol Parameter ICC ISB ISB1 Operating Power Supply Current Standby Power Supply Current Test Condition 71216S8 71216S9 71216S10 71216S12 Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Unit 330 30 25 -- -- -- 300 30 25 -- -- -- 290 30 25 -- -- -- 280 30 25 -- -- -- mA mA mA
3067 tbl 10
PWRDN VIH Outputs Open, VCC = Max., f = fMAX(3) PWRDN VIL, VIN VIH or VIL VCC = Max., f = fMAX(3)
Full Standby Power PWRDN VIL, VIN VHC or VLC(4) Supply Current VCC = Max., f = 0(3)
NOTES: 1. All values are maximum guaranteed values. 2. CS1 VIL, CS2 VIH. 3. fMAX =1/tCYC (all address inputs are cycling at fMAX). f = 0 means no address input lines are changing. 4. VHC = VCC - 0.2V, VLC = 0.2V
14.3
6
IDT71216 BiCMOS 16K x 15 CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V 5%, VCCQ = 5.0V 5%
OR
3.3V 0.3V, TA = 0 to 70C)
IDT71216S8 IDT71216S9 Min. -- -- 1 1 -- 0 1 2 -- 0 1 -- -- 2 Max. 11 9 -- 6 6 -- 6 -- 6 -- 6 9 7 -- IDT71216S10 Min. -- -- 1 1 -- 0 1 2 -- 0 1 -- -- 2 Max. 12 10 -- 6 6 -- 6 -- 6 -- 6 10 8 -- IDT71216S12 Min. -- -- 1 1 -- 0 1 2 -- 0 1 -- -- 2 Max. 14 12 -- 7 7 -- 7 -- 7 -- 7 12 10 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3067 tbl 11
Symbol Parameter Read Cycle tAAT Address Access Time Tag Bits tACST Chip Select Access Time Tag Bits tCLZ(1) tCHZ(1) tOET tOTLZ(1) tOTHZ(1) tTOH tOES tOSLZ(1) tOSHZ(1) tAAS tACSS tSOH Chip Select to Tag and Status Bits in Low-Z Chip Select to Tag and Status Bits in High-Z Output Enable to Tag Bits Valid Output Enable to Tag Bits in Low-Z Output Enable to Tag Bits in High-Z Tag Bit Hold from Address Change Output Enable to Status Bits Valid Output Enable to Status Bits in Low-Z Output Enable to Status Bits in High-Z Address Access Time Status Bits Chip Select Access Time Status Bits Status Bit Hold from Address Change
Min. -- -- 1 1 -- 0 1 2 -- 0 1 -- -- 2
Max. 10 8 -- 5 5 -- 5 -- 5 -- 5 8 6 --
NOTE: 1. This parameter is guaranteed with the AC Load (Figure 3) by device characterization, but is not production tested.
AC ELECTRICAL CHARACTERISTICS (1)
(VCC = 5.0V 5%, VCCQ = 5.0V 5%
Symbol Parameter Reset and Power Down Cycles tSR tHR tSRST tSHRS tRSMI tRSMV tRSHZ(2) tRSLZ(2) tPDSR tRHPL tRHWL tPD(2) tPU(2) tPDHZ(2) tPDLZ(2) tPUV tWHPL(2) tPUWL
OR
3.3V 0.3V, TA = 0 to 70C)
IDT71216S8 Min. Max. 4 1 -- 2 -- -- -- -- 30 1 90 -- 0 -- 0 -- 5 50 -- -- 50 -- 9 110 9 90 -- -- -- 50 -- 9 -- 50 -- -- IDT71216S9 Min. Max. 4 1 -- 2 -- -- -- -- 30 1 95 -- 0 -- 0 -- 5 50 -- -- 60 -- 10 120 10 100 -- -- -- 50 -- 10 -- 50 -- -- IDT71216S10 Min. Max. 4 1 -- 2 -- -- -- -- 30 1 95 -- 0 -- 0 -- 5 50 -- -- 60 -- 10 120 10 100 -- -- -- 50 -- 10 -- 50 -- -- IDT71216S12 Min. Max. 4 1 -- 2 -- -- -- -- 30 1 105 -- 0 -- 0 -- 5 50 -- -- 70 -- 12 130 12 110 -- -- -- 50 -- 12 -- 50 -- -- Unit ns ns ns ns ns ns ns ns ns CLK ns ns ns ns ns ns ns ns
3067 tbl 12
RESET Set-up Time RESET Hold Time
Status Bit Reset Time Status Bit Hold from RESET LOW
RESET LOW to MATCH and TA Invalid RESET HIGH to MATCH and TA Valid RESET LOW to TAG High-Z RESET HIGH to TAG Low-Z PWRDN Set-up to RESET LOW RESET HIGH to PWDRN LOW RESET HIGH to WET and WES LOW PWRDN LOW to Low Power Mode PWRDN HIGH to Active Power Mode PWRDN LOW to Outputs in High-Z PWRDN HIGH to Outputs in Low-Z PWRDN HIGH to Outputs Valid WET and WES HIGH to PWRDN LOW PWRDN HIGH to WET and WES Active
NOTES: 1. Power-down mode is intended to be used during extended time periods of device inactivity. 2. This parameter is guaranteed with the AC Load (Figure 3) by device characterization, but is not production tested.
14.3
7
IDT71216 BiCMOS 16K x 15 CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (1)
(VCC = 5.0V 5%, VCCQ = 5.0V 5% Symbol
tCYC tCH(2, 3) tCL(2, 3) tS tH tSA tHA tWMI tCKLZ(3) tCTV(4) tCSV(4) tCSH(3) tWHPL tPUWL Clock Cycle Time Clock Pulse HIGH Clock Pulse LOW
OR
3.3V 0.3V, TA = 0 to 70C)
IDT71216S8 IDT71216S9 IDT71216S10 IDT71216S12
Parameter
Min. Max.
15 4.5 4.5 3 1 3 1 -- 1.5 -- -- 0 5 50 -- -- -- -- -- -- -- 6 -- 9 8 -- -- --
Min. Max.
15 4.5 4.5 3 1 3 1 -- 1.5 -- -- 0 5 50 -- -- -- -- -- -- -- 7 -- 10 9 -- -- --
Min.
15 4.5 4.5 3 1 3 1 -- 1.5 -- -- 0 5 50
Max.
-- -- -- -- -- -- -- 7 -- 10 9 -- -- --
Min. Max. Unit
16.6 5 5 3 1 3 1 -- 1.5 -- -- 0 5 50 -- -- -- -- -- -- -- 8 -- 12 10 -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3067 tbl 14
Write Cycle and Clock Parameters
WET, WES, Chip Select, and Input Data Set-up Time WET, WES, Chip Select, and Input Data Hold Time
Address Set-up Time Address Hold Time CLK HIGH Write to MATCH and TA Invalid CLK HIGH Read to Outputs in Low-Z CLK HIGH Read to Tag Bits Valid CLK HIGH Write to Status Outputs Valid Status Output Hold from CLK HIGH Write
WET and WES HIGH to PWRDN LOW PWRDN HIGH to WET and WES Active
NOTES: 1. All Write cycles are synchronous and referenced from rising CLK. 2. This parameter is measured as a HIGH time above 2.0V and a LOW time below 0.8V. 3. This parameter is guaranteed with the AC Load (Figure 3) by device characterization, but is not production tested. 4. Addresses are stable prior to CLK transition HIGH.
14.3
8
IDT71216 BiCMOS 16K x 15 CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V 5%, VCCQ = 5.0V 5%
Symbol tADM tDAM tCSM tCMLZ(1) tCMHZ(1) tMHA tMHD tBHA tBHD tADB tDAB tCSB tOEBV tOBLZ(1) tOBHZ(1) tBYFH tBYHV tSB tHB tBIBL tBIBV tOEMI tOEMV tWRBH(2) tWRBV(2) tWMI tWMV(3) Parameter Address to MATCH Valid Data Input to MATCH Valid Chip Select to MATCH Valid Chip Select to MATCH in Low-Z Chip Select to MATCH in High-Z MATCH Valid Hold from Address MATCH Valid Hold from Data MATCH and TA Cycles -- -- -- 1 1 2 2 2 2 -- -- -- -- 0 1 -- -- 4 1.5 -- -- -- -- -- -- -- -- 8 8 8 -- 5 -- -- -- -- 9 9 9 6 -- 5 5 5 -- -- 6 6 6 7 6 6 7 8 -- -- -- 1 1 2 2 2 2 -- -- -- -- 0 1 -- -- 4 1.5 -- -- -- -- -- -- -- -- 9 9 9 -- 6 -- -- -- -- 10 10 10 6 -- 6 5 5 -- -- 6 6 7 8 7 7 7 9 -- -- -- 1 1 2 2 2 2 -- -- -- -- 0 1 -- -- 4 1.5 -- -- -- -- -- -- -- -- 10 10 10 -- 6 -- -- -- -- 11 11 11 7 -- 6 5 5 -- -- 7 7 7 8 7 7 7 10 -- -- -- 1 1 2 2 2 2 -- -- -- -- 0 1 -- -- 4 1.5 -- -- -- -- -- -- -- -- 12 12 12 -- 7 -- -- -- -- 13 13 13 8 -- 7 6 6 -- -- 8 8 8 10 8 8 8 12 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3067 tbl 15
OR
3.3V 0.3V, TA = 0 to 70C)
IDT71216S8 Min. Max. IDT71216S9 Min. Max. IDT71216S10 Min. Max. IDT71216S12 Min. Max. Unit
TA Valid Hold from Address TA Valid Hold from Data Address to TA Valid Data Input to TA Valid Chip Select LOW to TA Valid TAOE LOW to TA Valid TAOE LOW to TA in Low-Z TAOE HIGH to TA in High-Z TAH HIGH to Force TA HIGH TAH LOW to TA Valid TAIN Set-up Time TAIN Hold Time CLK HIGH TAIN LOW to TA LOW CLK HIGH TAIN HIGH to TA Valid OET LOW to MATCH and TA Invalid OET HIGH to MATCH and TA Valid W/R HIGH to TA HIGH W/R LOW to TA Valid CLK HIGH Write to MATCH and TA Invalid CLK HIGH Read to MATCH and TA Valid
NOTES: 1. This parameter is guaranteed with the AC Load (Figure 3) by device characterization, but is not production tested. 2. These parameters only apply when SFUNC is LOW and the internal WT bit is HIGH. 3. tADM, tDAM, tCSM and tADB, tDAB, tCSB must also be satisfied.
14.3
9
IDT71216 BiCMOS 16K x 15 CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Timing Reference Levels AC Test Load GND to 3.0V 3ns 1.5V 1.5V See Figs. 1, 2, 3, & 4
3067 tbl 16
AC TEST LOADS
VCCQ 893 Outputs 347 30pF *
VCCQ 893 Tag I/O 347 50pF *
3067 drw 03
3067 drw 04
Figure 1. AC Test Load
Figure 2. Tag I/O AC Test Load
* Including scope and jig capacitance
6
VCCQ
5
Tag I/O and Outputs 347
893
4 3 t (Typical, ns) 2 1
3067 drw 05
5pF*
Figure 3. AC Test Load (for tHZ and tLZ parameters )
* Including scope and jig capacitance
20 30
50
80 100 Capacitance (pF)
3067 drw 06
Figure 4. Lumped Capacitance Load, Typical Derating
14.3
10
STATUS WRITE TAG WRITE
TAG READ
CLK
A (0:13) tS tH tTOH tAAT tAAT
IDT71216 BiCMOS 16K x 15 CACHE-TAG RAM
VALID
VALID VALID
CS1
CS2 tS tH tCHZ(1) tACST tCLZ(1)
WET
tS tCTV tH tOTHZ(1) tCKLZ(1) tOTLZ(1) tOET
TIMING WAVEFORMS OF WRITE AND READ CYCLES
14.3
OET
Valid Input tAAS
TAG (0:11)
Valid Output tAAS
Valid Output
Valid Output
WES
tS tH Valid tCSV tCSH Valid tCHZ(1) Valid tACSS tCLZ(1) Valid Valid
3067 drw 07
tSOH
tSOH
VLDIN
DTYIN
WTIN
VLDOUT DTYOUT WTOUT
COMMERCIAL TEMPERATURE RANGE
11
NOTE: 1. Transition is measured 200mV from steady state.
CLK
A (0:13)
Valid Address
tADT tADM tMHA tTHA
IDT71216 BiCMOS 16K x 15 CACHE-TAG RAM
TAG (0:11)
Valid Match Data
CS1
tS tH tH tS tS
tDAT tDAM tMHD tTHD
CS2
WES
tS tH
TIMING WAVEFORMS OF MATCH AND TA FUNCTIONS
14.3
WET
tCMLZ(1)
OET
tOEMV tOTLZ(1) tCST tOEMI
TAH tTAHV tCSM tOETV
TAOE
tTAFH Valid TA Valid tWMI tWMV tWMI tWMV Valid Valid tCMHZ(1) tOTHZ(1) Valid Valid
TA
Valid
MATCH
Valid
MATCH Valid
Valid
Valid
Valid
3067 drw 08
COMMERCIAL TEMPERATURE RANGE
12
NOTE: 1. Transition is measured 200mV from steady state.
IDT71216 BiCMOS 16K x 15 CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORMS OF RESET FUNCTION
CLK tSR tHR
RESET
tPDSR
PWRDN
tSRST tSHRS VLDOUT DTYOUT WTOUT
tS
tRHWL
WES WET
tRSMI tRSMV VALID VALID tRSHZ(1) TAG (0:11)
3067 drw 09
TA
MATCH tRSLZ(1)
NOTE: 1. Transition is measured 200mV from steady state.
CLOCK TIMING WAVEFORM
tCH CLK 2.0V 2.0V
3067 drw 10
tCYC 0.8V
tCL 0.8V
TIMING WAVEFORMS OF TA AND TT1 SIGNAL
Applies when SFUNC is LOW, and the internal WT bit is HIGH
CLK tSTI tHTI
TAIN
tTITL TT1 tTHTH tTHTV tTITV
TA
TA Valid
TA Valid
3067 drw 11
14.3
13
IDT71216 BiCMOS 16K x 15 CACHE-TAG RAM
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORMS OF OES FUNCTION
OES
tOES tOSHZ(1) VLDOUT DTYOUT WTOUT
NOTE: 1. Transition is measured 200mV from steady state.
tOSLZ(1) Valid Output Valid Output
3067 drw 12
TIMING WAVEFORMS OF POWER DOWN FUNCTION
PWRDN
tWHPL CLK tRHPL tPUWL
RESET
tS tS
WET, WES
tPDHZ(1) TAG (0:10) tPDLZ(1) VLDOUT DTYOUT WTOUT Valid Status out tPUV Valid TAG out
TA
MATCH tPD ICC ISB
NOTE: 1. Transition is measured 200mV from steady state.
TA Valid
MATCH Valid tPU
3067 drw 13
ORDERING INFORMATION
IDT 71216 Device Type S Power XX Speed PF Package PF 8 9 10 12 Plastic Thin Quad Flatpack (PN80-1)
Speed in nanoseconds
3067 drw 14
14.3
14

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